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2022-10-03, 02:29
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#1 |
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"emily"
Nov 2021
us midwest
5 Posts |
PrimeNet rejects my computer's specs
i sent an email on this topic to primenet@mersenne.org about two weeks ago, but haven't received a response.
i'm attempting to run mprime on a system with an Intel Xeon Phi 7250. it reports the following specs: Code:
CPU Information: Intel(R) Xeon Phi(TM) CPU 7250 @ 1.40GHz CPU speed: 1485.25 MHz, 68 hyperthreaded cores CPU features: Prefetchw, SSE, SSE2, SSE4, AVX, AVX2, FMA, AVX512F L1 cache size: 68x32 KB, L2 cache size: 34x1 MB, L3 cache size: 4x4096 MB Code:
[Comm thread Sep 18 14:05] Updating computer information on the server [Comm thread Sep 18 14:05] URL: http://v5.mersenne.org/v5server/?v=0.95&px=GIMPS&t=uc&[redacted]&a=Linux64,Prime95,v30.8,build+16&c=Intel(R)+Xeon+Phi(TM)+CPU+7250+@+1.40GHz&f=Prefetch,SSE,SSE2,SSE4,AVX,AVX2,FMA,+AVX512F&L1=32&L2=1024&np=68&hp=4&m=15841&s=1485&h=24&r=1000&L3=4194304&[redacted] [Comm thread Sep 18 14:05] RESPONSE: [Comm thread Sep 18 14:05] pnErrorResult=7 [Comm thread Sep 18 14:05] pnErrorDetail=parameter L3: Invalid int value/precision '4194304' [Comm thread Sep 18 14:05] ==END== [Comm thread Sep 18 14:05] [Comm thread Sep 18 14:05] PrimeNet error 7: Invalid parameter [Comm thread Sep 18 14:05] parameter L3: Invalid int value/precision '4194304' [Comm thread Sep 18 14:05] Visit http://mersenneforum.org for help. [Comm thread Sep 18 14:05] Will try contacting server again in 70 minutes. this reads to me like a problem that requires a server-side fix, but if you've got a local workaround i can use in the meantime, i am all ears. Last fiddled with by emilymm on 2022-10-03 at 02:58 Reason: fixing whitespace |
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2022-10-03, 03:39
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#2 |
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P90 years forever!
Aug 2002
Yeehaw, FL
23×1,021 Posts |
Try again. Sorry, your email ended up in a spam folder.
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2022-10-03, 03:40
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#3 |
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P90 years forever!
Aug 2002
Yeehaw, FL
23×1,021 Posts |
BTW, there are a couple of folks here that can help best configure prime95 for a Xeon Phi.
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2022-10-03, 04:40
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#4 |
"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
11100110101012 Posts |
http://v5.mersenne.org/v5design/v5webAPI_0.97.html#uc says L3 is in units of KB.
So reporting "&L3=4194304" would mean 4 GiB of L3 cache. Not sure why the client would be sending that value. (One quadrant of 4?) The PrimeNet server may regard that as a too-large value for L3 cache size. Big Xeons are typically 55MB L3 or less. https://ark.intel.com/content/www/us...v4-family.html AMD Zen4 are ~80MB or less, depending partly on whose web page we believe. How, in your BIOS and (on which?) Linux, do you tell it to use the MCDRAM as L3 cache? I have not found a way to do that on the SuperMicro K1SPE motherboard and Windows 10. Xeon 7250, Windows 10 Pro 21H2, no DIMMs, only MCDRAM being used as main system memory. (If there were DIMMs installed, it does not treat MCDRAM as L3 cache, but as additional system ram, and gets confused how many cores and caches there are, and gets very slow compared to running on MCDRAM only.) Windows 10 divides many-core systems into processor groups of 64 logical cores or less. Code:
[Thu Nov 12 19:50:38 2020]
Compare your results to other computers at http://www.mersenne.org/report_benchmarks
Intel(R) Xeon Phi(TM) CPU 7250 @ 1.40GHz
CPU speed: 1400.23 MHz, 68 hyperthreaded cores
CPU features: Prefetchw, SSE, SSE2, SSE4, AVX, AVX2, FMA, AVX512F
L1 cache size: 68x32 KB, L2 cache size: 34x1 MB
L1 cache line size: 64 bytes, L2 cache line size: 64 bytes
Machine topology as determined by hwloc library:
Machine#0 (total=7027020KB, Backend=Windows, hwlocVersion=2.2.0, ProcessName=prime95.exe)
Package (total=7027020KB, CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=87, CPUModel="Intel(R) Xeon Phi(TM) CPU 7250 @ 1.40GHz", CPUStepping=1)
Group0#0 (total=7027020KB)
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0000000f)
PU#0 (cpuset: 0x00000001)
PU#1 (cpuset: 0x00000002)
PU#2 (cpuset: 0x00000004)
PU#3 (cpuset: 0x00000008)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x000000f0)
PU#4 (cpuset: 0x00000010)
PU#5 (cpuset: 0x00000020)
PU#6 (cpuset: 0x00000040)
PU#7 (cpuset: 0x00000080)
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x00000f00)
PU#8 (cpuset: 0x00000100)
PU#9 (cpuset: 0x00000200)
PU#10 (cpuset: 0x00000400)
PU#11 (cpuset: 0x00000800)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0000f000)
PU#12 (cpuset: 0x00001000)
PU#13 (cpuset: 0x00002000)
PU#14 (cpuset: 0x00004000)
PU#15 (cpuset: 0x00008000)
...
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0f000000,0x0)
PU#56 (cpuset: 0x01000000,0x0)
PU#57 (cpuset: 0x02000000,0x0)
PU#58 (cpuset: 0x04000000,0x0)
PU#59 (cpuset: 0x08000000,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0xf0000000,0x0)
PU#60 (cpuset: 0x10000000,0x0)
PU#61 (cpuset: 0x20000000,0x0)
PU#62 (cpuset: 0x40000000,0x0)
PU#63 (cpuset: 0x80000000,0x0)
Group0#1
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0000000f,,0x0)
PU#64 (cpuset: 0x00000001,,0x0)
PU#65 (cpuset: 0x00000002,,0x0)
PU#66 (cpuset: 0x00000004,,0x0)
PU#67 (cpuset: 0x00000008,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x000000f0,,0x0)
PU#68 (cpuset: 0x00000010,,0x0)
PU#69 (cpuset: 0x00000020,,0x0)
PU#70 (cpuset: 0x00000040,,0x0)
PU#71 (cpuset: 0x00000080,,0x0)
...
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0f000000,,,0x0)
PU#120 (cpuset: 0x01000000,,,0x0)
PU#121 (cpuset: 0x02000000,,,0x0)
PU#122 (cpuset: 0x04000000,,,0x0)
PU#123 (cpuset: 0x08000000,,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0xf0000000,,,0x0)
PU#124 (cpuset: 0x10000000,,,0x0)
PU#125 (cpuset: 0x20000000,,,0x0)
PU#126 (cpuset: 0x40000000,,,0x0)
PU#127 (cpuset: 0x80000000,,,0x0)
Group0#2
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0000000f,,,,0x0)
PU#128 (cpuset: 0x00000001,,,,0x0)
PU#129 (cpuset: 0x00000002,,,,0x0)
PU#130 (cpuset: 0x00000004,,,,0x0)
PU#131 (cpuset: 0x00000008,,,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x000000f0,,,,0x0)
PU#132 (cpuset: 0x00000010,,,,0x0)
PU#133 (cpuset: 0x00000020,,,,0x0)
PU#134 (cpuset: 0x00000040,,,,0x0)
PU#135 (cpuset: 0x00000080,,,,0x0)
...
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0f000000,,,,,0x0)
PU#184 (cpuset: 0x01000000,,,,,0x0)
PU#185 (cpuset: 0x02000000,,,,,0x0)
PU#186 (cpuset: 0x04000000,,,,,0x0)
PU#187 (cpuset: 0x08000000,,,,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0xf0000000,,,,,0x0)
PU#188 (cpuset: 0x10000000,,,,,0x0)
PU#189 (cpuset: 0x20000000,,,,,0x0)
PU#190 (cpuset: 0x40000000,,,,,0x0)
PU#191 (cpuset: 0x80000000,,,,,0x0)
Group0#3
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0000000f,,,,,,0x0)
PU#192 (cpuset: 0x00000001,,,,,,0x0)
PU#193 (cpuset: 0x00000002,,,,,,0x0)
PU#194 (cpuset: 0x00000004,,,,,,0x0)
PU#195 (cpuset: 0x00000008,,,,,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x000000f0,,,,,,0x0)
PU#196 (cpuset: 0x00000010,,,,,,0x0)
PU#197 (cpuset: 0x00000020,,,,,,0x0)
PU#198 (cpuset: 0x00000040,,,,,,0x0)
PU#199 (cpuset: 0x00000080,,,,,,0x0)
...
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0f000000,,,,,,,0x0)
PU#248 (cpuset: 0x01000000,,,,,,,0x0)
PU#249 (cpuset: 0x02000000,,,,,,,0x0)
PU#250 (cpuset: 0x04000000,,,,,,,0x0)
PU#251 (cpuset: 0x08000000,,,,,,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0xf0000000,,,,,,,0x0)
PU#252 (cpuset: 0x10000000,,,,,,,0x0)
PU#253 (cpuset: 0x20000000,,,,,,,0x0)
PU#254 (cpuset: 0x40000000,,,,,,,0x0)
PU#255 (cpuset: 0x80000000,,,,,,,0x0)
Group0#4
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0000000f,,,,,,,,0x0)
PU#256 (cpuset: 0x00000001,,,,,,,,0x0)
PU#257 (cpuset: 0x00000002,,,,,,,,0x0)
PU#258 (cpuset: 0x00000004,,,,,,,,0x0)
PU#259 (cpuset: 0x00000008,,,,,,,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x000000f0,,,,,,,,0x0)
PU#260 (cpuset: 0x00000010,,,,,,,,0x0)
PU#261 (cpuset: 0x00000020,,,,,,,,0x0)
PU#262 (cpuset: 0x00000040,,,,,,,,0x0)
PU#263 (cpuset: 0x00000080,,,,,,,,0x0)
L2 (size=1024KB, linesize=64, ways=16, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x00000f00,,,,,,,,0x0)
PU#264 (cpuset: 0x00000100,,,,,,,,0x0)
PU#265 (cpuset: 0x00000200,,,,,,,,0x0)
PU#266 (cpuset: 0x00000400,,,,,,,,0x0)
PU#267 (cpuset: 0x00000800,,,,,,,,0x0)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
Core (cpuset: 0x0000f000,,,,,,,,0x0)
PU#268 (cpuset: 0x00001000,,,,,,,,0x0)
PU#269 (cpuset: 0x00002000,,,,,,,,0x0)
PU#270 (cpuset: 0x00004000,,,,,,,,0x0)
PU#271 (cpuset: 0x00008000,,,,,,,,0x0)
Prime95 64-bit version 30.3, RdtscTiming=1
If that's not already too much, there's more at https://mersenneforum.org/showpost.p...72&postcount=8, https://mersenneforum.org/showpost.p...7&postcount=22 |
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2022-10-03, 11:27
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#5 |
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"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
112×61 Posts |
I think 4Gi =232 or anything larger may be the problem.
The PrimeNet API spec says: Code:
2.0 Parameter Data Types Elementary data types and precisions are expected and returned by the API. All data types have character set and length constraints (minima and maxima) determined by type, API requirements, or both. Data Type Max Precision Comment integer 32 bits decimal-encoded unsigned; other/future API versions may be 64 bits Thanks for reporting the issue. Now that its existence has been identified, something may be done about it. Have you tried a workaround of removing all DIMMs? That would force using the MCDRAM as main ram instead of L3 cache that gets reported. Last fiddled with by kriesel on 2022-10-03 at 11:35 |
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2022-10-03, 11:54
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#6 |
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"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
112·61 Posts |
NUMA & PrimeNet API
I don't recall seeing anything in the PrimeNet API spec for describing NUMA attributes of a computer.
Number of NUMA nodes for example. "NUMA" does not appear in the spec posted. "node" appears in 7.1 & 8.1 (reserved for future system purposes). Going to https://www.mersenne.org/cpus/ then looking at the detail for the one system shows my 7250 as follows Code:
Public Name (max 20 characters) Kilroy was here too Last Activity 2022-10-03 06:26, Last Updated 2022-10-02 22:27, Registered 2021-01-03 01:15 GUID (redacted) Software Version Windows64,Prime95,v30.8,build 14 Model Intel(R) Xeon Phi(TM) CPU 7250 @ 1.40GHz Features 68 core, hyperthreaded, Prefetch,SSE,SSE2,SSE4,AVX,AVX2,FMA, AVX512F Speed 0.402 GHz (3.280 GHz P4 effective equivalent) L1/L2 Cache 32 / 1024 KB Computer Memory 16261 MB configured usage 11264 MB day / 11264 MB night Reliability, Confidence 0.98, 10.0 Reset, I fixed the hardware Status Trusted software version Hours per day 24 hours (day memory use starts 07:30 and ends 23:30) @emilymm what does your 7250 show there? Last fiddled with by kriesel on 2022-10-03 at 12:02 |
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2022-10-03, 17:20
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#7 | |||
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"emily"
Nov 2021
us midwest
510 Posts |
Quote:
that is what it looks like yes, as in my first post at the top of the thread it reports to the user "L1 cache size: 68x32 KB, L2 cache size: 34x1 MB, L3 cache size: 4x4096 MB" and to the server L1/2/3 sizes of 32, 1024, and 4194304. Quote:
I am also using a SuperMicro K1SPE, there is a bios option for it. in the Advanced tab under Uncore configuration, you can configure the clustering mode and memory mode. Memory mode controls whether the MCDRAM is used as cache, as additional RAM, or as a hybrid with part of the MCDRAM as cache and part as dedicated RAM. Clustering mode controls the memory architecture. the default is "all2all", which evenly distributes the memory accesses to each of the four memory controllers on the chip. this is bad for latency, but is usually the best option for software which isn't well-tuned to this chip. there are also hemisphere and quadrant modes, and variants of those (SNC-2 and SNC-4) which are identical to hemisphere and quadrant but expose the memory architecture to the host OS as NUMA information, so that applications can then control their thread affinity and memory allocations to reduce memory latency as much as possible. those latter two modes are not compatible with Windows, as I understand (i wouldn't know for sure; i do not use Windows). Quote:
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2022-10-03, 18:27
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#8 |
Sep 2002
Database er0rr
10001100100012 Posts |
Hey, I am running a Phi 7250. I hooked it up to PrimeNet recently for the winter months with the latest mprime. It chose 32 workers -- perfect! -- and I chose "152" for each of the workers. It will take over 55 days to complete, but I get 32 results! Hopefully one will be a prime!
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2022-10-03, 18:39
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#9 | ||
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"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
738110 Posts |
Quote:
I haven't seen that in the manual, and the pdf reader's search function comes up empty for "uncore". As did Ernst and I looking in the actual BIOS menus, as I recall. I think it was grayed out if found at all. I'll try again at some point. What version AMI BIOS do you have on your 7250 equipped K1SPE? What distro and version Linux is working for you? Have you tried installing any GPUs? Quote:
Emily's roadblock may be that mprime is reporting 222 KiB L3 cache (a quadrant of the MCDRAM), which the server can convert to 232 bytes (and get by overflow, 0), since the PrimeNet API web page states max integer value is 32 bit unsigned. Last fiddled with by kriesel on 2022-10-03 at 19:08 |
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2022-10-03, 18:47
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#10 | |
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Sep 2002
Database er0rr
3·1,499 Posts |
Quote:
I use numactl --preffered=1 ./mprime  I just checked -- mine is a 7210 and so is not aware of all that fancy clustering options in BIOS, like all2all, quadrant, hemisphere.
Last fiddled with by paulunderwood on 2022-10-03 at 19:19 |
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2022-10-03, 19:13
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#11 | |||||
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"emily"
Nov 2021
us midwest
5 Posts |
Quote:
the exact path is Advanced -> Chipset Configuration -> North Bridge -> Uncore Configuration. they are the first two options in that page. it would be very strange for them to be greyed out, as this is considered a standard configuration option for these processors. Quote:
`dmidecode` reports version 2.0, revision 5.12, from 12/05/2017. Quote:
i am using Gentoo, and currently it's on kernel 5.15.59, though i am about to upgrade to the latest 6.0 release. Quote:
i have a Radeon RX Vega 56 in it right now, but i am only using it for additional monitor connections, and i intentionally do not have Mesa set up for it, so there is no 3d acceleration or OpenCL being used. the reason behind that is that i am currently using this machine as my primary workstation, and one of the projects i am working on is a software-rendered Vulkan implementation. Quote:
i would presume that was the issue, yes (it's now working) |
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