Nocona's (and Prescott's) AMD64 compatibility

Dresdenboy · 2004-02-18, 06:53

.. could mean, that any clients developed for AMD64 (just using the extended SSE2 registers or even the hybrid modular/floating transform) on the GIMPS Opteron could also be used on these CPUs when they hit the market.

The dedicated multiplier in Prescott has (AFAIK) 4 cycles latency and a throughput of 1/cycle for 32bit. That's very close to 3/1 on K8 (Opteron/A64). So the 64bit mul could be also in the range of 4-5/2 as seen on current AMD64 CPUs.

An advantage of the Intel chips would be, that they are able to issue up to 2 integer instructions (x86 inst. which need just 1 uOp) in combination with an SSE2 instruction while the K8 can only issue one integer inst. in this case. And then we have the higher clock speed, which usually helps for applications, which are optimized for throughput.

Disadvantages are longer cache and instruction latencies, a still smaller L1, and a possibly lower throughput for several 64bit integer instructions.

ColdFury · 2004-02-19, 02:52

George mentioned a while ago that the 64-bit registers could speed up the factoring code. I know you guys ran into a bottleneck with the FFTs. Maybe you should work on the factoring code?

frmky · 2004-02-19, 05:25

As you may be aware, Intel has released the developer's guide for their x86-64 cpu at http://developer.intel.com/technolog...ons/300834.htm. Not knowing enough about processors to decypher it myself, how compatible with AMD64 is it? What did Intel leave out, and what new things did they throw in?

ColdFury · 2004-02-19, 08:47

It's almost identical, except for a lack of 3DNow (naturally).

Dresdenboy · 2004-05-14, 07:42

Quote:

Originally Posted by ColdFury

George mentioned a while ago that the 64-bit registers could speed up the factoring code. I know you guys ran into a bottleneck with the FFTs. Maybe you should work on the factoring code?

George surely meant the 64bit GPRs. These would surely speed up the code. If the factoring code has a rather regular loop structure (didn't look at it yet) it could be mixed with the FFT code similar to a hybrid modular/floating point transform. There are enough pipeline "bubbles" to do that and the Opteron doesn't have SMT to fill them. At least the K9 will have it.

There is also a workaround (which means a lot of work) for the bottleneck. But the reason for it's strong effect on FFT performance is lack of registers (as usual on x86

) - so the 64bit mode could also help here.

E_tron · 2004-05-14, 13:25

Quote:

Originally Posted by frmky

...how compatible with AMD64 is it?...

knowing intel, they will try to be as incompatible with AMD as possible. Both intel and AMD's 64 specs look similar, however i believe that intel will try to make their 64 specs perform poorly on AMD hardware. Why would intel need AMD standards? Intel has the market share.

Dresdenboy · 2004-05-14, 14:50

Intels 64bit extension (for Nocona) is 99% compatible. The main differences (besides missing 3DNow!, which is no problem because of a correctly zeroed 3DNow! bit in CPUID) are a few, less used instructions, which AMD modified/added to newer versions of the x86-64 documentation, which Intel used.

http://www.mdronline.com/watch/watch...77000000000000

2004-02-18, 06:53	#1
Dresdenboy Apr 2003 Berlin, Germany 19² Posts	Nocona's (and Prescott's) AMD64 compatibility .. could mean, that any clients developed for AMD64 (just using the extended SSE2 registers or even the hybrid modular/floating transform) on the GIMPS Opteron could also be used on these CPUs when they hit the market. The dedicated multiplier in Prescott has (AFAIK) 4 cycles latency and a throughput of 1/cycle for 32bit. That's very close to 3/1 on K8 (Opteron/A64). So the 64bit mul could be also in the range of 4-5/2 as seen on current AMD64 CPUs. An advantage of the Intel chips would be, that they are able to issue up to 2 integer instructions (x86 inst. which need just 1 uOp) in combination with an SSE2 instruction while the K8 can only issue one integer inst. in this case. And then we have the higher clock speed, which usually helps for applications, which are optimized for throughput. Disadvantages are longer cache and instruction latencies, a still smaller L1, and a possibly lower throughput for several 64bit integer instructions.

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2004-02-19, 02:52	#2
ColdFury Aug 2002 2⁶·5 Posts	George mentioned a while ago that the 64-bit registers could speed up the factoring code. I know you guys ran into a bottleneck with the FFTs. Maybe you should work on the factoring code?

2004-02-19, 05:25	#3
frmky Jul 2003 So Cal 4043₈ Posts	As you may be aware, Intel has released the developer's guide for their x86-64 cpu at http://developer.intel.com/technolog...ons/300834.htm. Not knowing enough about processors to decypher it myself, how compatible with AMD64 is it? What did Intel leave out, and what new things did they throw in?

2004-02-19, 08:47	#4
ColdFury Aug 2002 2⁶×5 Posts	It's almost identical, except for a lack of 3DNow (naturally).

2004-05-14, 14:50	#7
Dresdenboy Apr 2003 Berlin, Germany 19² Posts	Intels 64bit extension (for Nocona) is 99% compatible. The main differences (besides missing 3DNow!, which is no problem because of a correctly zeroed 3DNow! bit in CPUID) are a few, less used instructions, which AMD modified/added to newer versions of the x86-64 documentation, which Intel used. http://www.mdronline.com/watch/watch...77000000000000