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#1 |
Sep 2002
1916 Posts |
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Hi,
does anyone already got some data on the influence of L3 cache size (2M/6M/8M) on p95 iteration times for the AMD Phenom2 architecture? |
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#2 |
Jun 2003
32×17 Posts |
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AFAIK, George has not added any code to Prime95 Version 25.9 which takes advantage of the L3 cache to increase performance. Prime95 version 25.9 build 4 recognizes the L3 cache, but does not take advantage of it yet.
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#3 |
Jul 2006
Calgary
6518 Posts |
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#4 | ||
Sep 2002
110012 Posts |
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