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#34 |
Aug 2002
3A16 Posts |
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The CPUs aren't generally "changeable" in an end-user system. If they were they would run the risk of becoming unusable after a failed or faulty update. CPU makers like to push that risk to some other part of the system. So at power-up it's always in the same state. The microcode lives in ROM and RAM near the IF/ID stages. It can be updated at boot from EFI/BIOS and/or by the OS. A few Xeon variants do come with an accessory FPGA, but it doesn't affect the CPU internals.
Perhaps bringing this back to the original subject of this thread, the microcode implementation likely has a big influence on AVX512 performance. Did the questions around random-read performance get sufficiently answered experimentally? If not, want questions would you want to ask someone at Intel about memory access in combination with AVX512? |
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#35 | |
"/X\(‘-‘)/X\"
Jan 2013
29·101 Posts |
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