Preliminary Skylake-X benchmark

[Prime95]

Originally Posted by ET_

Prime95 reports the Skylake chips on Google Compute Engine as having 2506 MHz.

Don't trust prime95's measurement of clock speed. That code was based on Intel's suggested code around the Pentium 3/4 era.

[science_man_88]

Originally Posted by xx005fs

That might be an advantage. However, I feel like that GPUs like Titan V draws like 300 watts under load if you don't overclock and it does under 1ms/it for 85M exponents, in which a consumer ryzen/i5 draws around 65 watt and does 6 ms/it and that would yield much better efficiency for the Titan V. Also, I found out that Vega 56 could get a lot of undervolt done and then it would achieve 2.06ms/it at about 200W board power. Hoping for GPU implementation in prime95 for the future as that would identify my devices and put their credit up on the site instead of manual testing.

thats 300 mJ /it, 390 mJ/it , and 412 mJ/it respectively. which means 100%, ~77%, ~ 73% as efficient respectively.

[xx005fs]

Originally Posted by science_man_88

thats 300 mJ /it, 390 mJ/it , and 412 mJ/it respectively. which means 100%, ~77%, ~ 73% as efficient respectively.

Thanks for the energy calculation. But my bad for putting 65W for cpu as that's pretty rare when you consider the SoC power and other stuff, I think a more reasonable system power draw would be around at least 90W. So AMD GPU might have better efficiency than CPU and I would honestly prefer the higher power draw on GPUs because they get PRP tests done way faster than consumer CPU.

[NookieN]

Originally Posted by Mysticial

I'm less convinced that the throttling logic takes up enough die area to be reused for something else. Is this just speculation, or is there a source somewhere? This would imply changes to the silicon, and given all the binning that's done, I would think it's better to have everything come off the same assembly line so the parts can be sold to any market depending on how they turn out.

That's correct. First of all, it says right on AWS's marketing that the C5 instances support turbo. Turbo and throttling are two sides of the same coin from a logic perspective. Yes unlocked parts let you defeat the turbo suggestions, but otherwise turbo and throttle are using the power and temperature sensors to balance clock rate and heat.

And second, spinning new silicon is massively expensive. Even a small change to a design means new masks to send to the fab, new fab lots, re-validation of the design, and new testing protocols in the assembly-test factories. They use the silicon they have, and like you said, find a market for everything that someone will buy.

[ET_]

Originally Posted by Prime95

Don't trust prime95's measurement of clock speed. That code was based on Intel's suggested code around the Pentium 3/4 era.

It's a way to approximately measure CPU speed. On another computer I have this:

Intel Celeron N2840 @ 2.16GHz 100 MHz

And indeed it works on Prime95 like a 100MHz PC

[ATH]

CPU-Z can tell you the cpu speed:
https://www.cpuid.com/softwares/cpu-z.html

Then you can add the line to local.txt
CpuSpeed=s

where s is the speed in MHz.

[ewmayer]

Originally Posted by NookieN

And second, spinning new silicon is massively expensive. Even a small change to a design means new masks to send to the fab, new fab lots, re-validation of the design, and new testing protocols in the assembly-test factories. They use the silicon they have, and like you said, find a market for everything that someone will buy.

I believe - someone correct me if I'm wrong - most modern super-complex desins contain a small amount of (relatively area-inefficient) programmable logic in addition to the super-dense fixed logic precisely because [a] it is so difficult to get all the bugs out of modern CPUs at fab time, and [b] as you note above, major redesigns are expensive. Note the programmable logic could come in either or both of 2 forms: field-programmable and mask-programmable. The former is the most flexible but super-inefficient in terms of area, whereas the latter provides a good compromise for high-volume chips, since it requires only a few mask layers to be tweaked.

[chalsall]

Originally Posted by ewmayer

The former is the most flexible but super-inefficient in terms of area, whereas the latter provides a good compromise for high-volume chips, since it requires only a few mask layers to be tweaked.

I would argue that once you have your masks in the fab, you don't want to change those too often.

And, so, even though it might be less efficient in terms of surface area for the logic, it makes sense to make changes in the microcode to fix issues encountered once the kit is "in the field".

Unless and until you find something fundamentally wrong with the wiring....

[ewmayer]

Originally Posted by chalsall

And, so, even though it might be less efficient in terms of surface area for the logic, it makes sense to make changes in the microcode to fix issues encountered once the kit is "in the field".

Do you happen to know where the Intel CPU microcode resides? In flash memory or in a PLA?

[chalsall]

Originally Posted by ewmayer

Do you happen to know where the Intel CPU microcode resides?

No.

[retina]

Originally Posted by ewmayer

Do you happen to know where the Intel CPU microcode resides?

In the CPU

But since the µCode can be updated at runtime I suspect the live version of the µCode is in RAM, and the stored version is (probably) in ROM.