![]() |
![]() |
#1 |
"/X\(‘-‘)/X\"
Jan 2013
11·281 Posts |
![]()
The latest slide to leak is that Zen may have up to 8 channels of DDR4.
http://www.extremetech.com/extreme/2...ddr4-interface |
![]() |
![]() |
![]() |
#2 |
Dec 2014
3×5×17 Posts |
![]()
My 12 core AMD chip has 2 NUMA nodes and each node has their own memory channels.
(Each NUMA node owns some of the RAM and one node accessing the other nodes memory is something like 50% slower.) One way AMD could have 32-core and 8 DDR4 channels, is to have 4 NUMA nodes of 8 cores each. Each node has 2 DDR4 memory channels. Of course, this is just speculation. The question for prime95 is how many FPU the 32-cores will have? The 12-core AMD has 6 FPU. |
![]() |
![]() |
![]() |
#3 |
∂2ω=0
Sep 2002
República de California
5·2,351 Posts |
![]() |
![]() |
![]() |
![]() |
#4 | |
Just call me Henry
"David"
Sep 2007
Liverpool (GMT/BST)
37×163 Posts |
![]() Quote:
|
|
![]() |
![]() |
![]() |
#5 | |
Jan 2013
6810 Posts |
![]() Quote:
|
|
![]() |
![]() |
![]() |
#6 |
"/X\(‘-‘)/X\"
Jan 2013
11×281 Posts |
![]()
The latest news is that AMD engineers have achieved better than the 40% IPC improvement talked about earlier, and that it's somewhere between Broadwell and Skylake.
The 8 core (16 thread) chip should have a 95 watt TDP and be out in October. http://wccftech.com/amd-zen-cpu-8-co...ching-october/ I think I may pre-order one when possible. |
![]() |
![]() |
![]() |
#7 | |
"Kieren"
Jul 2011
In My Own Galaxy!
236568 Posts |
![]() Quote:
|
|
![]() |
![]() |
![]() |
#8 |
P90 years forever!
Aug 2002
Yeehaw, FL
1FDF16 Posts |
![]()
I would wait. IMO, Bulldozer's AVX implementation was so stupendously bad that they probably need to triple IPC (or more) before they become competitive again.
Last fiddled with by Prime95 on 2016-03-14 at 21:28 |
![]() |
![]() |
![]() |
#9 | |
"/X\(‘-‘)/X\"
Jan 2013
11·281 Posts |
![]() Quote:
The chip's lead architect, Jim Keller, also lead the K8 architecture and co-authored X86-64. So I am hopeful it is well done. Time will tell though! |
|
![]() |
![]() |
![]() |
#10 | |
"/X\(‘-‘)/X\"
Jan 2013
11·281 Posts |
![]() Quote:
I hope they call everything Zen. AMD already has excitement around that name. The 8 channel, 32 core chips come from the CERN slides. Given that Zen is structured around modules of 4 cores, it would make sense if they have one memory channel per module. Of course, with less than perfect yields, I bet they'll sell chips with cores and the consummate amount of L3 cache disabled, which will hopefully improve the memory bandwidth situation. I'm curious what the officially supported DDR4 frequency will be. |
|
![]() |
![]() |
![]() |
#11 |
Feb 2016
UK
3×149 Posts |
![]()
I hope I'm wrong with what I'm about to write...
From the earlier link, there is suggestion that a Zen core has two 128-bit FP units that can join together to do 256-bit. Haswell has two 256-bit units per core. Assuming they're equally efficient per clock, does that mean you'd need two Zen cores to match one Haswell? So Zen possibly having 8 cores might only be around parity with an existing Intel quad. Dual channel ram for 8 cores sounds weak to me. Put it this way, say if Zen floating point is as good as Haswell per core, its memory bandwidth requirements are going to be serious. This might be mitigated if all cores work on the same task. Has there been any speculation on possible cache sizes? A generous dose of last level cache could help a lot. So, I really hope either the info is wrong, or my interpretation is wrong, as I'd love to see more viable prime-finding CPUs than the current game of which Intel do I try next. |
![]() |
![]() |
![]() |
Thread Tools | |
![]() |
||||
Thread | Thread Starter | Forum | Replies | Last Post |
Intel Processor Speculations | Mark Rose | Hardware | 109 | 2017-10-13 16:55 |
Cannonlake speculations | henryzz | Hardware | 0 | 2017-03-03 19:49 |