Google open-source silicone manufacturing

preda · 2022-11-13, 09:07

According to https://www.phoronix.com/news/Google-GloFo-Sponsored-Si
Google is covering the cost of initial production of some open-source silicone projects.

Could we produce a design for specialized HW that would be useful for our project? i.e. that would be faster, more efficient, and/or cheaper than GPUs.

We should probably start with something as simple as possible initially, and iterate from there.

retina · 2022-11-13, 09:14

Quote:

Originally Posted by preda

... silicone projects.

Google now pays for our breast implants.

LaurV · 2022-11-13, 10:19

yeah, and you have to pay for my keyboard now, in case it gets damaged from the spilled coffee!

you could notify me before!

Joking apart, how about a 96 bits modular multiplier? (I think 128 bits is a bit more complicate?)
Or full modular exponentiator?
One register to hold the modulus, few more to hold the operands and a lot of VHDL... (for who knows it...)
I would buy such a chip if the price/performance worth.
I may also partially sponsor the initial hardware (FPGA, tools) if anybody convinces me that (s)he is skilled enough to do it.

kriesel · 2022-11-13, 10:30

Power efficiency and throughput would be poor. It's on 180nm process tech, a far cry from 10nm or 7nm used in recent CPUs or GPUs, or even some rather old hardware. Core 2 (2006-2012) was 65 nm to 45 nm. https://en.wikipedia.org/wiki/Intel_Core_2

LaurV · 2022-11-13, 11:38

Not necessary. All Cortex M (like STM32Fxxxx) are 180nm, and they only switched to 90nm for the newer (G and C) series. And you get 480MHz clocks, 32 bits ARM (general processing), and 80uA/MHz power burning. ASICs for mining are other example.

Don't confuse general (x86) processors with dedicated, simple toys. We don't need (and not able to make, most probably) complex thingies like a CPU. We can start simple, make a modular multiplier, that can be tested in some FPGA and duplicated, put hundreds of them in a virtex, and kill few TF ranges. Then step-up, making an exponentiator. It will help a lot with TF, and we can get a lot of experience.

Then we see...

(small steps)

xilman · 2022-11-13, 13:50

Suggestion: an ALU which uses RNS rather than classical multiple precision, where RNS is the Residue Number System.

Addition, subtraction and multiplication are inherently carry-free and so trivially parallizable. In particular, multiplication runs in time O(n).
Modular multiplication can be implemented in Montgomery arithmetic, though it does require O(n²) time.

Division and comparison (other than testing for equality) are tricky and detecting overflow is almost impossible.

Instructions for converting between RNS and conventional MP representations would also be necessary. Division, for instance, could be done on the cpu rather than on the co-processor.

Gordon · 2022-12-05, 23:34

Quote:

Originally Posted by preda

According to https://www.phoronix.com/news/Google-GloFo-Sponsored-Si
Google is covering the cost of initial production of some open-source silicone projects.

Could we produce a design for specialized HW that would be useful for our project? i.e. that would be faster, more efficient, and/or cheaper than GPUs.

We should probably start with something as simple as possible initially, and iterate from there.

Bit late to the party, but I'd like to mfaktc as a custom chip...

28add11 · 2022-12-11, 19:38

This sounds like it could have good potential. The only question is if anyone wants to learn Verilog/VHDL

!
It might be good to start practicing on some cheap FPGAs before we get into the weeds of things. I'm fairly new to the project and the math so I don't know what should be focused on but this does sound really interesting.

2022-11-13, 09:07	#1
preda "Mihai Preda" Apr 2015 2²×19² Posts	Google open-source silicone manufacturing According to https://www.phoronix.com/news/Google-GloFo-Sponsored-Si Google is covering the cost of initial production of some open-source silicone projects. Could we produce a design for specialized HW that would be useful for our project? i.e. that would be faster, more efficient, and/or cheaper than GPUs. We should probably start with something as simple as possible initially, and iterate from there.

2022-11-13, 10:19	#3
LaurV Romulan Interpreter "name field" Jun 2011 Thailand 2829₁₆ Posts	yeah, and you have to pay for my keyboard now, in case it gets damaged from the spilled coffee! you could notify me before! Joking apart, how about a 96 bits modular multiplier? (I think 128 bits is a bit more complicate?) Or full modular exponentiator? One register to hold the modulus, few more to hold the operands and a lot of VHDL... (for who knows it...) I would buy such a chip if the price/performance worth. I may also partially sponsor the initial hardware (FPGA, tools) if anybody convinces me that (s)he is skilled enough to do it. Last fiddled with by LaurV on 2022-11-13 at 10:26 Reason: tyops

2022-11-13, 11:38	#5
LaurV Romulan Interpreter "name field" Jun 2011 Thailand 3×23×149 Posts	Not necessary. All Cortex M (like STM32Fxxxx) are 180nm, and they only switched to 90nm for the newer (G and C) series. And you get 480MHz clocks, 32 bits ARM (general processing), and 80uA/MHz power burning. ASICs for mining are other example. Don't confuse general (x86) processors with dedicated, simple toys. We don't need (and not able to make, most probably) complex thingies like a CPU. We can start simple, make a modular multiplier, that can be tested in some FPGA and duplicated, put hundreds of them in a virtex, and kill few TF ranges. Then step-up, making an exponentiator. It will help a lot with TF, and we can get a lot of experience. Then we see... (small steps) Last fiddled with by LaurV on 2022-11-13 at 11:39

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2022-11-13, 10:30	#4
kriesel "TF79LL86GIMPS96gpu17" Mar 2017 US midwest 2×29×127 Posts	Power efficiency and throughput would be poor. It's on 180nm process tech, a far cry from 10nm or 7nm used in recent CPUs or GPUs, or even some rather old hardware. Core 2 (2006-2012) was 65 nm to 45 nm. https://en.wikipedia.org/wiki/Intel_Core_2

2022-11-13, 13:50	#6
xilman Bamboozled! "𒉺𒌌𒇷𒆷𒀭" May 2003 Down not across 10110110001011₂ Posts	Suggestion: an ALU which uses RNS rather than classical multiple precision, where RNS is the Residue Number System. Addition, subtraction and multiplication are inherently carry-free and so trivially parallizable. In particular, multiplication runs in time O(n). Modular multiplication can be implemented in Montgomery arithmetic, though it does require O(n²) time. Division and comparison (other than testing for equality) are tricky and detecting overflow is almost impossible. Instructions for converting between RNS and conventional MP representations would also be necessary. Division, for instance, could be done on the cpu rather than on the co-processor.

2022-12-11, 19:38	#8
28add11 "Nicholas" Dec 2022 Alberta, Canada 2×3 Posts	This sounds like it could have good potential. The only question is if anyone wants to learn Verilog/VHDL ! It might be good to start practicing on some cheap FPGAs before we get into the weeds of things. I'm fairly new to the project and the math so I don't know what should be focused on but this does sound really interesting.