Use of a virtual private server (VPS) - normally a web server

[drkirkby]

I've got a virtual private server, VPS for my company website.



https://www.kirkbymicrowave.co.uk/


when the CPUs are not busy serving the website, they are busy running mprime. That's a pretty small VPS, with only two cores. It is currently 90% completed a PRP test of the exponent 110,048,903



https://www.mersenne.org/report_expo...0048903&full=1


and 97% completed 110.061,157


https://www.mersenne.org/report_expo...0061157&full=1


The load average is close to 2.0, which is to be expected.



I just bought another VPS contract, which has 8 cores. That's crunching it way though



https://www.mersenne.org/report_expo...0232041&full=1
https://www.mersenne.org/report_expo...0241563&full=1


but despite the 8-cores, the load average on this is only about 3 - see attachment. I've tried changing the number of workers and cores, but nothing seem to be giving me a decent load average. I realise web servers are not designed as supercomputers. but I'm amazed how poor that VPS is, given it has 8 cores and 24 GB RAM. Those PRP tests are expected to have taken 24 days in total, which is quite handy as there's a 30-day money back period on the contract.

[Prime95]

Start a throughput benchmark, abort it after a few seconds.

In results.bench.txt there should be a description from hwloc as to your hardware. Post that -- something fishy may be going on.

[drkirkby]

[dkirkby@jackdaw tmp]$ cat results.bench.txt
[Fri Mar 12 11:50:46 2021]
Compare your results to other computers at http://www.mersenne.org/report_benchmarks
Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz
CPU speed: 2785.56 MHz, 8 cores
CPU features: Prefetch, SSE, SSE2, SSE4, AVX, AVX2, FMA
L1 cache size: 8x32 KB, L2 cache size: 8x1 MB, L3 cache size: 8x36608 KB
L1 cache line size: 64 bytes, L2 cache line size: 64 bytes
Machine topology as determined by hwloc library:
 Machine#0 (total=24586304KB, DMIProductName="VMware Virtual Platform", DMIProductVersion=None, DMIBoardVendor="Intel Corporation", DMIBoardName="440BX Desktop Reference Platform", DMIBoardVersion=None, DMIBoardAssetTag=, DMIChassisVendor="No Enclosure", DMIChassisType=1, DMIChassisVersion=N/A, DMIChassisAssetTag="No Asset Tag", DMIBIOSVendor="Phoenix Technologies LTD", DMIBIOSVersion=6.00, DMIBIOSDate=12/12/2018, DMISysVendor="VMware, Inc.", Backend=Linux, LinuxCgroup=/, OSName=Linux, OSRelease=5.3.18-lp152.63-default, OSVersion="#1 SMP Mon Feb 1 17:31:55 UTC 2021 (98caa86)", HostName=localhost, Architecture=x86_64, hwlocVersion=2.0.4, ProcessName=mprime)
  Package#0 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000001)
            PU#0 (cpuset: 0x00000001)
  Package#2 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000002)
            PU#1 (cpuset: 0x00000002)
  Package#4 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000004)
            PU#2 (cpuset: 0x00000004)
  Package#6 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000008)
            PU#3 (cpuset: 0x00000008)
  Package#8 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000010)
            PU#4 (cpuset: 0x00000010)
  Package#10 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000020)
            PU#5 (cpuset: 0x00000020)
  Package#12 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000040)
            PU#6 (cpuset: 0x00000040)
  Package#14 (CPUVendor=GenuineIntel, CPUFamilyNumber=6, CPUModelNumber=63, CPUModel="Intel(R) Xeon(R) Gold 6230R CPU @ 2.10GHz", CPUStepping=0)
    L3 (size=36608KB, linesize=64, ways=11, Inclusive=0)
      L2 (size=1024KB, linesize=64, ways=16, Inclusive=0)
        L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
          Core#0 (cpuset: 0x00000080)
            PU#7 (cpuset: 0x00000080)
Prime95 64-bit version 30.3, RdtscTiming=1

[Prime95]

The hwloc topology looks good.

My guess is the V in VPS means you are sharing that nice physical CPU with some other customers running CPU intensive tasks.

[drkirkby]

Originally Posted by Prime95

The hwloc topology looks good.

My guess is the V in VPS means you are sharing that nice physical CPU with some other customers running CPU intensive tasks.

Thank you.



The CPU is certainly shared, as the CPU is 26-core, and I only have 8 of them. A computer could have up to two of those CPUs, so potentially up to 52 cores. But I thought I would get 8 of them all to myself. Someone pointed out that 8 cores might not be on the same CPU, so I could have 5 on one CPU and 3 on another, which would not be ideal.



As someone else pointed out, with the virtualisation anything can be hidden. I don't really know what's going on.



Anyway, I just took out a contract with https://contabo.com/


They don't have a good reputation, but I only want it as a backup server, in case the Ionos ones fails. So far this year, the uptime for the Ionos VPS has been 99.998%, but last year there was a 14-hour outage, so I want to have a backup. The cheap one in Germany will do as a backup, and can crunch GIMPS when it is not serving my company website.



Dave

[drkirkby]

The output shown by mprime is a cache of 8 x 33608 kB. I don't think that's right. I believe the total cache size is 35.75 MB. That I believe is shared among all 26 cores.

[Happy5214]

Originally Posted by drkirkby

The output shown by mprime is a cache of 8 x 33608 kB. I don't think that's right. I believe the total cache size is 35.75 MB. That I believe is shared among all 26 cores.

You read that printout wrong. That says 8x36608 KB (second digit 6), which does equal 8x35.75 MB.

[drkirkby]

Originally Posted by Happy5214

You read that printout wrong. That says 8x36608 KB (second digit 6), which does equal 8x35.75 MB.

Okay, apologies, but it does not change the underlying point I was making.



The printout is implying there are 8 x 35.75 MB = 286 MB of cache available to me. But the cache size on that Xeon is not 286 MB, nor anywhere near that much.



https://ark.intel.com/content/www/us...-2-10-ghz.html


I believe all 26 cores access the same 37.75 MB of cache - they don't each have a separate cache.

[chalsall]

Originally Posted by drkirkby

I believe all 26 cores access the same 37.75 MB of cache - they don't each have a separate cache.

Correct.

Virtualization can't magically make more hardware. All it does is oversubscribe what's available.

[Happy5214]

Originally Posted by drkirkby

I believe all 26 cores access the same 37.75 MB of cache - they don't each have a separate cache.

Oh, yeah, it's an L3 cache, so by rule it's shared across the cores. That report is clearly a misprint.

[drkirkby]

Originally Posted by Happy5214

Oh, yeah, it's an L3 cache, so by rule it's shared across the cores. That report is clearly a misprint.

Is there anywhere to report such a bug?

Dave