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Old 2021-04-06, 16:08   #1
M344587487
 
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Default Ice Lake Xeons (10nm, up to 40 cores)

https://www.phoronix.com/scan.php?pa...xeon-icl&num=1


  • 10nm
  • Up to 40 cores
  • 8 channel DDR4-3200
  • 270W TDP
  • AVX-512
  • PCIe 4.0



The top intel part has 24 less cores than Epyc but intel has AVX-512 to its advantage. The 40 core part has 60MB of what I believe is L3 cache, if it's unified it may be a decent advantage for some workloads even if dwarfed in size by Epyc's 256MB. IMO a step in the right direction, the main question is how well they can mass produce it.
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Old 2021-04-06, 17:35   #2
mackerel
 
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Other sources show 60MB L3, or typically 1.5MB/core of L3 plus 1.25MB/core of L2 which is non-inclusive so that will also count.

The cache is unified... as much as it was since Skylake server versions when the mesh layout was introduced. You're still going to have remote slices at varying distances so performance scaling isn't quite as good as it could be.

Ian Cutress of Anandtech had estimated die size and assuming same defect rate as TSMC's 7N process, came up with a figure of 56%. Of course, many of the non-perfect ones may be re-used as lower core count parts.
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Old 2021-04-06, 20:55   #3
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Quote:
Originally Posted by M344587487 View Post

*]270W TDP
Wow. You'll need an Ice Lake to keep it cool...
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Old 2021-04-06, 22:58   #4
mackerel
 
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Zen 3 Epycs run to 280W TDP, and not limited to the top core count parts. Guess that is just where servers are currently.
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