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Old 2006-11-07, 06:26   #1
crash893
 
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Default Japanese researchers build 512-core math coprocessor

http://www.blogsmithmedia.com/www.en...1/kaisou_e.jpg

http://www.engadget.com/2006/11/06/j...h-coprocessor/
"
While we're just getting used to dual-cores and have our eyes on those upcoming quad-core chips, Japanese computer scientists at the University of Tokyo have built a 500MHz 512-core math co-processor chip that can perform up to 512 billion floating-point operations per second. The Grape DR chip is designed to fit on a PCI-X card and act as a secondary chip for the main CPU. The project, which has been ongoing since 1989, expects to reach two petaflops (that's two quadrillion, or 2,000,000,000,000,000) floating-point operations per second sometime around 2008. No doubt that Intel, which is planning on an 80-core processor by 2011, is watching this research very very closely.

[Via Channel Register]"
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Old 2006-11-07, 13:41   #2
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WOW - would be interesting to run Prime95 on that thing!
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Old 2006-11-07, 16:08   #3
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Quote:
Originally Posted by crash893 View Post
The Grape DR chip is designed to fit on a PCI-X card and act as a secondary chip for the main CPU. The project, which has been ongoing since 1989, expects to reach two petaflops (that's two quadrillion, or 2,000,000,000,000,000) floating-point operations per second sometime around 2008
The GRAPE people have always been on the forefront of massively parallel computation. They have to compute Newton's equations of motion for huge collections of bodies to high accuracy, and because of that they have to use algorithms that scale quadratically with the number of masses.

GIMPS can't use any of their work; this is another case where single precision floating point is enough. Besides, the LL test doesn't look anything like massively parallel force computation, which is the only thing these systems do.

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Old 2006-11-07, 16:10   #4
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Quote:
Originally Posted by crash893 View Post
http://www.blogsmithmedia.com/www.en...1/kaisou_e.jpg

http://www.engadget.com/2006/11/06/j...h-coprocessor/
"
While we're just getting used to dual-cores and have our eyes on those upcoming quad-core chips, Japanese computer scientists at the University of Tokyo have built a 500MHz 512-core math co-processor chip that can perform up to 512 billion floating-point operations per second. The Grape DR chip is designed to fit on a PCI-X card and act as a secondary chip for the main CPU. The project, which has been ongoing since 1989, expects to reach two petaflops (that's two quadrillion, or 2,000,000,000,000,000) floating-point operations per second sometime around 2008. No doubt that Intel, which is planning on an 80-core processor by 2011, is watching this research very very closely.

[Via Channel Register]"
I wonder how the cores will handle cache, bus, and memory contention?

How much memory will each have? Will the cache be multi-ported? etc.

This architecture is probably terrific for small problems that easy fit
in cache. I wonder how it will handle NFS. Certainly one can't give a
separate NFS thread to each core!!!!!
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Old 2006-11-07, 16:37   #5
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what about factoring
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Old 2006-11-07, 16:39   #6
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Quote:
Originally Posted by jasonp View Post
this is another case where single precision floating point is enough.
I wouldn't trust the result of doing 2,000,000,000,000,000 operations (done in just one second) in single precision math. The rounding error would be very high.
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Old 2006-11-07, 17:17   #7
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Quote:
Originally Posted by alpertron View Post
I wouldn't trust the result of doing 2,000,000,000,000,000 operations (done in just one second) in single precision math. The rounding error would be very high.
Even in double precision it will be high. The expected error for
doing 2 x 10^15 additions is about 4.47 x 10^7 ULP.
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Old 2006-11-08, 01:30   #8
jasonp
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Quote:
Originally Posted by R.D. Silverman View Post
I wonder how the cores will handle cache, bus, and memory contention?

How much memory will each have? Will the cache be multi-ported? etc.

This architecture is probably terrific for small problems that easy fit
in cache. I wonder how it will handle NFS. Certainly one can't give a
separate NFS thread to each core!!!!!
The only GRAPE-related paper I have in my archives is Kamai et. al, "GRAPE-5: A Special-Purpose Computer for N-Body Simulation". Later GRAPE cores actually use IEEE single precision, but this paper gives a lot of detail on the system. Earlier systems had rows of cabinets of processing boards, connected to an Alpha.
Quote:
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what about factoring
Factoring doesn't look much like physics either

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Last fiddled with by jasonp on 2006-11-08 at 01:32
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Old 2006-11-08, 19:26   #9
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>Each processor will contain one simple floating-point arithmetic unit and
>integer arithmetic unit, and small local memory (256 double-precision words)

So, double precision for this project.
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Old 2006-11-12, 04:42   #10
moo
 
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does it make eggs.
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