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2011-08-20, 08:16   #12
axn

Jun 2003

2×5×467 Posts

Quote:
 Originally Posted by R. Gerbicz Division in one cycle? For arbitrary large p values, say for p=10^999+7 ? Maybe in your dream. Read some math and English books.
Never mind arbitrary p values. I want to know which CPU architecture has a single cycle div even for "normal" values.

 2011-08-20, 08:48 #13 JohnFullspeed   May 2011 France 7×23 Posts Informatic books Read informatic book about RISC processor before laught You learn that in a RISC processor ALL the opcodes have thje same duration Actually the processor make sometimes 2 operations in a cycle The problem is when the value (in bits) is greater than the register 64 bits)10^20 The value is store in a vector and the computatiopn is make by vector value i/e let n be store like this 123456 ,7891234,256 (near 25 digits) if you want to divide by 65433 you make something like this rest= 256 shl 31 rest:=rest or 7891234 rest= rest div 65433 rest:= rest shl 31 rrest:=rest or 7891234 rest= rest div 65433 rest:= rest shl 31 on a RISC 7 op-code so 7 cyvles When you add 32 bits at your value (4 200 000 000) you only add 2 cycles.. Intel say: div 100 cycles SHR 5 cycles It for this reason that a G5 is speeder than the last Intel I only have a G5 not a Power7 http://support.apple.com/kb/sp96 http://en.wikipedia.org/wiki/POWER7 Last fiddled with by JohnFullspeed on 2011-08-20 at 09:00 Reason: Correct umerus error (not all sorry)
2011-08-20, 13:12   #14
science_man_88

"Forget I exist"
Jul 2009
Dumbassville

20C016 Posts

Quote:
 Originally Posted by axn Never mind arbitrary p values. I want to know which CPU architecture has a single cycle div even for "normal" values.
http://en.wikipedia.org/wiki/Reduced...g#RISC_and_x86

looks like most of what I have that I could ever hook up have them if it's RISC I have a PlayStation 2,N64, iPod, and my computer sounds like that listing involving HP Compaq etc. as it's processor went obsolete in 2007 at last read.

Last fiddled with by science_man_88 on 2011-08-20 at 13:16

2011-08-20, 13:42   #15
science_man_88

"Forget I exist"
Jul 2009
Dumbassville

100000110000002 Posts

Quote:
 Originally Posted by science_man_88 http://en.wikipedia.org/wiki/Reduced...g#RISC_and_x86 looks like most of what I have that I could ever hook up have them if it's RISC I have a PlayStation 2,N64, iPod, and my computer sounds like that listing involving HP Compaq etc. as it's processor went obsolete in 2007 at last read.
forgot my wii as well and I think I have another thing I won't list.

2011-08-20, 13:53   #16
CRGreathouse

Aug 2006

5,869 Posts

Quote:
 Originally Posted by JohnFullspeed Read informatic book about RISC processor before laught You learn that in a RISC processor ALL the opcodes have thje same duration
Not as of the 7400. Look at the docs:
http://developer.apple.com/hardwared...rformance.html

It specifically mentions division as a multi-cycle instruction.

I can't find good documents like the Intel guides to give more specific values, but I wouldn't compare a 32-bit 7-cycle division instruction to a 64-bit 30-cycle division instruction on a processor with twice the clocks too readily.

Last fiddled with by CRGreathouse on 2011-08-20 at 13:54

2011-08-20, 14:53   #17
axn

Jun 2003

2×5×467 Posts

Quote:
 Originally Posted by CRGreathouse Not as of the 7400. Look at the docs: http://developer.apple.com/hardwared...rformance.html It specifically mentions division as a multi-cycle instruction. I can't find good documents like the Intel guides to give more specific values, but I wouldn't compare a 32-bit 7-cycle division instruction to a 64-bit 30-cycle division instruction on a processor with twice the clocks too readily.
/rant mode on
The claim of a single-cycle division doesn't pass the smell test. I mean, if it could be done, intel, amd et al would be doing it themselves. Just becuase you're RISC doesn't mean you have magical circuitry available to do single-cycle divs. Now, "pure" RISCs won't even have divide instruction. But any processor that implements div in h/w must either implement a multi-cycle version or must have a really reaaaaally long cycle
/rant mode off

@CRG - Where did the 7-cycle 32 bit division & 30-cycle 64-bit division come from?

 2011-08-20, 19:10 #18 JohnFullspeed   May 2011 France 16110 Posts Sorry I don't found the English translation http://fr.wikipedia.org/wiki/Reduced...n_set_computer Au contraire, les processeurs RISC qui étaient utilisés sur des calculateurs plus puissants se sont vu ajouter des instructions du type MULADD (multiplication + addition), instruction la plus utilisée dans le calcul vectoriel et matriciel. Ces instructions câblées en dur ne prenaient qu'un cycle pour multiplier 2 registres, y ajouter un autre registre et sauvegarder le résultat soit dans l'un de ces registres, soit dans un autre. C'est le cas par exemple dans l'architecture PowerPC, qui a équipé les Macintosh de 1994 à 2006, ou la BeBox, qui fut en 1995 le premier micro-ordinateur à double processeur. Little quesstion in 1995 motorola include a two cycles division in the CISC processor 15 years afterr why not Inbtel But the only true result id how many time to make 10000 or 1090000 of division i/e G1 := Random($fffffFFFfffff)+1; G2 := Random($ffFFFfffffff)+1 ; while G2 >G1 do G2:= Random(\$ffffffFFFffff)+1 ; a1 := GetTickCount; for i:= 1 to 5000000 do begin G1:=G1+i; // 3689641221786411 G3 :=G1 div G2; // 45089156699671 time: 343 /600(600 =1seconde end; a1 := GetTickCount-a1; The theory id one cycle for a div but the reality is other PS: Intel never do RISC..... Jhon
2011-08-20, 21:11   #19
CRGreathouse

Aug 2006

5,869 Posts

Quote:
 Originally Posted by axn @CRG - Where did the 7-cycle 32 bit division & 30-cycle 64-bit division come from?

Oops, I meant 19 rather than 7.

30 is my recollection of what one CISC (Phenom II?) takes to do division.

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