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2007-05-18, 22:27   #23
Cruelty

May 2005

31348 Posts

Quote:
 Originally Posted by S485122 Ok, the conclusion is then that a QuadCore is worth 3 cores with the P965 chipset, 2.6 with 975 and only 2 cores with the nVidia chipsets. Since memory is the bottleneck, memory capable of running 2:1 that is 8500 or 1067 MHz is a must .
The tests each of us has performed are not comparable so your claim is not valid I'm afraid

 2007-05-19, 02:22 #24 dsouza123     Sep 2002 2·331 Posts The Barcelona (server), or Phenom (desktop) quad cores speeds are to be 2.6, 2.7, 2.8 and 2.9 GHz. The AM2 socket for 2.6, 2.7, 2.9 and the 2.8 Quad FX on socket F. The prefetch will be 32 bytes, doubling the 16 bytes from previous CPUs.
2007-05-19, 07:59   #25
S485122

"Jacob"
Sep 2006
Brussels, Belgium

24·109 Posts

Quote:
 Originally Posted by Cruelty The tests each of us has performed are not comparable so your claim is not valid I'm afraid
If I look at the benchmark pages I find iteration times of 44,3 ms for 2048K exponents, my Q67 with the 8500 memory uses an average of 53,5 ms for each of the four instances and 42,9 ms if only one instance is running. So I even get 42,9/53,5*4 = 3,2 cores out of it. My AVERAGE iteration times are better than the BEST times from the benchmark and this is, AFAIK, due to the chipset used.

The same system used with 5400 memory had iteration times of 84 ms. The iteration times are almost exactly proportional to the memory speed. And since the memory used is among the fastest on the market for this architecture*, it is my conclusion that the memory controller/bus needs to be enhanced to provide a sufficient data flow for the Intel Quads.

As George said in a post Prime95 benchmarks are not the best way to benchmark a system for real life throughput, it is better to use real tests.

Jacob

*There is DDR2 10000 memory on the market but the difference with 8500 is only about 17%. DDR3 and DDR4 would be a solution to this problem if that memory really has a triple or quadruple data flow.

Last fiddled with by S485122 on 2007-05-19 at 07:59

2007-05-19, 08:41   #26
fivemack
(loop (#_fork))

Feb 2006
Cambridge, England

11001001010012 Posts

Quote:
 Originally Posted by S485122 *There is DDR2 10000 memory on the market but the difference with 8500 is only about 17%. DDR3 and DDR4 would be a solution to this problem if that memory really has a triple or quadruple data flow.
Unfortunately, DDR3 is double-rate memory, albeit with faster official clock speeds, lower power and a more exciting name. There will be DDR3-1333 memory available soon (but horribly expensive - launch price something like $500 per pair of 1GB modules), which is 10.5GB/sec/channel and goes nicely with the 1333MHz bus which is being introduced soon. http://www.anandtech.com/memory/showdoc.aspx?i=2989 has a review. What chip-set are you using with the DDR2 8500 memory? 2007-05-19, 15:36 #27 S485122 "Jacob" Sep 2006 Brussels, Belgium 24·109 Posts Quote:  Originally Posted by fivemack What chip-set are you using with the DDR2 8500 memory? P965 in a Asus P5B-E Plus board. 2007-05-22, 20:35 #28 Uncwilly 6809 > 6502 """"""""""""""""""" Aug 2003 101×103 Posts 3·47·71 Posts Quote:  Originally Posted by jasong If Prime95 processes a lot of data(though it becomes unimportant a few hundredths of a second later), and therefore has a bottleneck, would it not be better to seek out a worthy low bandwidth project and strategically distribute that project, along with Prime95, among the cores? That is why some folks run T-F and L-L concurrently. The T-F can generally stay in cache, while L-L needs main mem. 2007-05-28, 07:37 #29 drew Jun 2005 2×191 Posts Quote:  Originally Posted by R.D. Silverman Time is money. An extra$260 is a pittance when you need the capability NOW. Some of us have larger price elasticities.
That would be inelasticity.

2007-05-28, 08:23   #30
xilman
Bamboozled!

"𒉺𒌌𒇷𒆷𒀭"
May 2003
Down not across

22×3×11×83 Posts

Quote:
 Originally Posted by drew That would be inelasticity.
I'm not so sure.

If I want something now, rather than later, the range of prices I'm prepared to pay now is large. If my cost constraints are less flexible (i.e more inelastic) I have to wait until the product is on sale at a price I'm prepared to pay.

Paul

2007-05-28, 08:59   #31
drew

Jun 2005

2·191 Posts

Quote:
 Originally Posted by xilman I'm not so sure. If I want something now, rather than later, the range of prices I'm prepared to pay now is large. If my cost constraints are less flexible (i.e more inelastic) I have to wait until the product is on sale at a price I'm prepared to pay. Paul
Price elasticity is a well-defined economic concept. An elastic demand curve means the quantity demanded depends heavily on the price of the product.

Silverman made it clear that he wants a new processor, regardless of the price. This inelasticity means he's not easily influenced by the price of the product.

Last fiddled with by drew on 2007-05-28 at 09:04

2007-05-28, 16:49   #32
Richard Cameron

Mar 2005

2·5·17 Posts
intertemporal consumer choice

Quote:
 Originally Posted by R.D. Silverman Time is money. An extra \$260 is a pittance when you need the capability NOW.
this reads to me as a statement of Mr Silverman's time_preference It is his Discount_rate that is very high.

2007-05-28, 19:48   #33
drew

Jun 2005

2·191 Posts

Quote:
 Originally Posted by Richard Cameron this reads to me as a statement of Mr Silverman's time_preference It is his Discount_rate that is very high.
True, but that's beside the point. The original comment was regarding price elasticity.

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