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Old 2007-10-14, 20:39   #4
Dresdenboy
 
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Apr 2003
Berlin, Germany

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My assumption is, that they implemented DP in a way similar to what has been done in Cell's SPEs. Full featured DP with the same throughput as SP calculations or even half the throughput (filling the registers with 2 doubles instead of 4 singles) would cost a few hundred million transistors more and need a lot of power.

A software emulation via driver/CTM compiler would probably be far from being useful (since this could have been done already).
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