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Old 2007-07-05, 23:08   #4
Prime95
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Aug 2002
Yeehaw, FL

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I haven't given it serious thought, but would the following idea work?

In Knuth Vol 2, I think Knuth states there is a hardware multiply algorithm that operates in linear time. If it is pipeline-able, then would it be possible to use the standard recursive turn-one-big-multiply-into-3-half-size-multiplies until you got down to say 10,000 bit chunks, then feed these 10,000 bit chunks to the pipelined FPGA multiply algorithm.
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